Conventional nonvolatile semiconductor memories, such as flash electrically erasable programmable read only memories (flash EEPROMs), typically comprise a floating gate memory cell, which includes a source region, a drain region and a channel region formed in a semiconductor substrate, and a floating gate formed above the substrate between the channel region and a control gate. A voltage differential is created in the cell when a high voltage is applied to the control gate while the channel region is kept at a low voltage. This voltage difference causes electrons to move from the channel region to the floating gate through a phenomenon known as tunneling, thus charging the floating gate. This movement of electrons is referred to as programming.
FIG. 1 depicts a typical flash memory cell, wherein a pair of source/drain regions 20 and a channel region 30 are formed in a semiconductor substrate 10. A floating gate 50 is formed, usually of polysilicon, above the channel region 30, with a tunnel oxide layer 40 in between. A dielectric film 60, known as an "ONO layer" comprising a bottom silicon oxide layer 61, a silicon nitride layer 62 and a top silicon oxide layer 63, is typically formed on top of the floating gate 50. After formation of the top oxide layer 63, it is cleaned, as by chemical cleaning, typically employing an acid or by plasma techniques. A polysilicon control gate 70 is then formed on top oxide layer 63, followed by formation of a tungsten silicide (WSi) contact layer 80.
The top oxide layer 63 is typically relatively thin, for example, about 55 .ANG. or less, and becomes even thinner due to the chemical cleaning procedure. If the top oxide layer is thinned excessively, the distance between the floating gate 50 and the subsequently formed control gate 70 is sufficiently reduced to adversely affect the performance of the finished device, particularly the "data retention" of the flash memory; i.e., the length of time the floating gate 50 is able to store a charge. Data retention is a function of the thickness of the ONO film 60. The current industry standard for data retention of a flash memory cell is 100,000 hours (about 11.4 years). However, if the top oxide layer 63 is reduced by greater than about 10% below the design rule for the semiconductor device, leakage will occur from the floating gate 50 to the control gate 70, thereby decreasing device data retention below the standard. Thus, the tolerance for error in the processing of the top oxide layer 63 (its "process window"), especially during the cleaning process, is extremely narrow.
Furthermore, the problem of excessive thinning of the top oxide 63 becomes even more critical on scaling the device to smaller dimensions, in response to the increasing demand for miniaturization of electronic components and reduction of the power requirements of flash memory devices. As the flash memory is scaled down, and the thickness of the ONO film 60 is correspondingly reduced, deposition of its component oxide layers 61, 63 is more difficult to control due to inherent limitations of the deposition process, which results in oxide layers of lesser quality.
There exists a need for a method of manufacturing a composite dielectric layer of a flash memory device without reducing the data retention of the finished device below design requirements. There also exists a continuing need for a method of manufacturing a composite interpoly dielectric layer with improved control and greater accuracy.